/*	$NetBSD: imx21-clock.h,v 1.1.1.1 2017/06/15 20:14:23 jmcneill Exp $	*/

/*
 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

#ifndef __DT_BINDINGS_CLOCK_IMX21_H
#define __DT_BINDINGS_CLOCK_IMX21_H

#define IMX21_CLK_DUMMY			0
#define IMX21_CLK_CKIL			1
#define IMX21_CLK_CKIH			2
#define IMX21_CLK_FPM			3
#define IMX21_CLK_CKIH_DIV1P5		4
#define IMX21_CLK_MPLL_GATE		5
#define IMX21_CLK_SPLL_GATE		6
#define IMX21_CLK_FPM_GATE		7
#define IMX21_CLK_CKIH_GATE		8
#define IMX21_CLK_MPLL_OSC_SEL		9
#define IMX21_CLK_IPG			10
#define IMX21_CLK_HCLK			11
#define IMX21_CLK_MPLL_SEL		12
#define IMX21_CLK_SPLL_SEL		13
#define IMX21_CLK_SSI1_SEL		14
#define IMX21_CLK_SSI2_SEL		15
#define IMX21_CLK_USB_DIV		16
#define IMX21_CLK_FCLK			17
#define IMX21_CLK_MPLL			18
#define IMX21_CLK_SPLL			19
#define IMX21_CLK_NFC_DIV		20
#define IMX21_CLK_SSI1_DIV		21
#define IMX21_CLK_SSI2_DIV		22
#define IMX21_CLK_PER1			23
#define IMX21_CLK_PER2			24
#define IMX21_CLK_PER3			25
#define IMX21_CLK_PER4			26
#define IMX21_CLK_UART1_IPG_GATE	27
#define IMX21_CLK_UART2_IPG_GATE	28
#define IMX21_CLK_UART3_IPG_GATE	29
#define IMX21_CLK_UART4_IPG_GATE	30
#define IMX21_CLK_CSPI1_IPG_GATE	31
#define IMX21_CLK_CSPI2_IPG_GATE	32
#define IMX21_CLK_SSI1_GATE		33
#define IMX21_CLK_SSI2_GATE		34
#define IMX21_CLK_SDHC1_IPG_GATE	35
#define IMX21_CLK_SDHC2_IPG_GATE	36
#define IMX21_CLK_GPIO_GATE		37
#define IMX21_CLK_I2C_GATE		38
#define IMX21_CLK_DMA_GATE		39
#define IMX21_CLK_USB_GATE		40
#define IMX21_CLK_EMMA_GATE		41
#define IMX21_CLK_SSI2_BAUD_GATE	42
#define IMX21_CLK_SSI1_BAUD_GATE	43
#define IMX21_CLK_LCDC_IPG_GATE		44
#define IMX21_CLK_NFC_GATE		45
#define IMX21_CLK_LCDC_HCLK_GATE	46
#define IMX21_CLK_PER4_GATE		47
#define IMX21_CLK_BMI_GATE		48
#define IMX21_CLK_USB_HCLK_GATE		49
#define IMX21_CLK_SLCDC_GATE		50
#define IMX21_CLK_SLCDC_HCLK_GATE	51
#define IMX21_CLK_EMMA_HCLK_GATE	52
#define IMX21_CLK_BROM_GATE		53
#define IMX21_CLK_DMA_HCLK_GATE		54
#define IMX21_CLK_CSI_HCLK_GATE		55
#define IMX21_CLK_CSPI3_IPG_GATE	56
#define IMX21_CLK_WDOG_GATE		57
#define IMX21_CLK_GPT1_IPG_GATE		58
#define IMX21_CLK_GPT2_IPG_GATE		59
#define IMX21_CLK_GPT3_IPG_GATE		60
#define IMX21_CLK_PWM_IPG_GATE		61
#define IMX21_CLK_RTC_GATE		62
#define IMX21_CLK_KPP_GATE		63
#define IMX21_CLK_OWIRE_GATE		64
#define IMX21_CLK_MAX			65

#endif