/* $NetBSD: ixgbe_osdep.c,v 1.4.8.5 2023/10/13 18:20:30 martin Exp $ */

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/*$FreeBSD: head/sys/dev/ixgbe/ixgbe_osdep.c 327031 2017-12-20 18:15:06Z erj $*/

#include <sys/cdefs.h>
__KERNEL_RCSID(0, "$NetBSD: ixgbe_osdep.c,v 1.4.8.5 2023/10/13 18:20:30 martin Exp $");

#include "ixgbe_osdep.h"
#include "ixgbe.h"

inline device_t
ixgbe_dev_from_hw(struct ixgbe_hw *hw)
{
	return ((struct ixgbe_softc *)hw->back)->dev;
}

u16
ixgbe_read_pci_cfg(struct ixgbe_hw *hw, u32 reg)
{
	pci_chipset_tag_t  pc = hw->back->osdep.pc;
	pcitag_t           tag = hw->back->osdep.tag;

	switch (reg % 4) {
	case 0:
		return pci_conf_read(pc, tag, reg) & __BITS(15, 0);
	case 2:
		return __SHIFTOUT(pci_conf_read(pc, tag, reg - 2),
		    __BITS(31, 16));
	default:
		panic("%s: invalid register (%" PRIx32, __func__, reg);
		break;
	}
}

void
ixgbe_write_pci_cfg(struct ixgbe_hw *hw, u32 reg, u16 value)
{
	pci_chipset_tag_t  pc = hw->back->osdep.pc;
	pcitag_t           tag = hw->back->osdep.tag;
	pcireg_t old;

	switch (reg % 4) {
	case 0:
		old = pci_conf_read(pc, tag, reg) & __BITS(31, 16);
		pci_conf_write(pc, tag, reg, value | old);
		break;
	case 2:
		old = pci_conf_read(pc, tag, reg - 2) & __BITS(15, 0);
		pci_conf_write(pc, tag, reg - 2,
		    __SHIFTIN(value, __BITS(31, 16)) | old);
		break;
	default:
		panic("%s: invalid register (%" PRIx32, __func__, reg);
		break;
	}

	return;
}

inline u32
ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
{
	return bus_space_read_4(((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_tag,
	    ((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_handle, reg);
}

inline void
ixgbe_write_reg(struct ixgbe_hw *hw, u32 reg, u32 val)
{
	bus_space_write_4(((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_tag,
	    ((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_handle,
	    reg, val);
}

inline u32
ixgbe_read_reg_array(struct ixgbe_hw *hw, u32 reg, u32 offset)
{
	return bus_space_read_4(((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_tag,
	    ((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_handle,
	    reg + (offset << 2));
}

inline void
ixgbe_write_reg_array(struct ixgbe_hw *hw, u32 reg, u32 offset, u32 val)
{
	bus_space_write_4(((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_tag,
	    ((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_handle,
	    reg + (offset << 2), val);
}

inline void
ixgbe_write_barrier(struct ixgbe_hw *hw)
{
	bus_space_barrier(((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_tag,
	    ((struct ixgbe_softc *)hw->back)->osdep.mem_bus_space_handle,
	    0, ((struct ixgbe_softc *)hw->back)->osdep.mem_size,
	    BUS_SPACE_BARRIER_WRITE);
}